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Stereo, Single Supply 16-, 18- and 20-Bit Sigma-Delta DACs AD1857/AD1858
PRODUCT OVERVIEW
FEATURES Low Cost, High Performance Stereo DACs 128 Times Oversampling Interpolation Filter Multibit Modulator with Triangular PDF Dither Discrete Time and Continuous Time Analog Reconstruction Filters Extremely Low Out-of-Band Energy Buffered Outputs with 2 k Output Load Drive 94 dB Dynamic Range, -90 dB THD+N Performance Digital De-emphasis and Mute 0.1 C Maximum Phase Linearity Deviation Continuously Variable Sample Rate Support Power-Down Mode 16-, 18- and 20-Bit I2S-Justified, Left-Justified Modes Offered on AD1857 Accepts 24-Bit Word 16-Bit Right-Justified and DSP Serial Port Modes Offered on AD1858 Single +5 V Supply 20-Pin SSOP Package APPLICATIONS Digital Cable TV and Direct Broadcast Satellite Set-Top Decoder Boxes Video Laser Disk, Video CD and CD-I Players High Definition Televisions, Digital Audio Broadcast Receivers CD, CD-R, DAT, DCC and MD Players Digital Audio Workstations, Computer Multimedia Products
The AD1857/AD1858 are complete single-chip stereo digital audio playback components. They each comprise an advanced digital interpolation filter, a revolutionary "linearity-compensated" multibit sigma-delta () modulator with dither, a jitter-tolerant DAC, switched capacitor and continuous time analog filters and analog output drive circuitry. Other features include digital de-emphasis processing and mute. The AD1857/AD1858 support continuously variable sample rates with essentially linear phase response, and support 50/15 s digital de-emphasis intended for "Redbook" 44.1 kHz sample frequency playback from Compact Discs. The user must provide a master clock that is synchronous with the left/right clock at 256 or 384 times the intended sample frequency. The AD1857/AD1858 have a simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The AD1857 serial data input port can be configured in either 16-bit, 18-bit or 20-bit left-justified or I2S-justified modes. The AD1858 serial data input port can be configured in either 16-bit right-justified or DSP serial port compatible modes. The AD1857/AD1858 accept serial audio data in MSB first, twos-complement format. A power-down mode is offered to minimize power consumption when the device is inactive. The AD1857/AD1858 operate from a single +5 V power supply. They are fabricated on a single monolithic integrated circuit and housed in 20-pin SSOP packages for operation over the temperature range 0C to +70C.
FUNCTIONAL BLOCK DIAGRAM
DIGITAL SUPPLY 2 COMMON MODE CLOCK MODE CLOCK IN
16-/18-/20-BIT DIGITAL DATA INPUT
3
SERIAL DATA INTERFACE
AD1857/AD1858
128x INTERPOLATION FILTER 128x INTERPOLATION FILTER
VOLTAGE REFERENCE
CLOCK CIRCUIT
SERIAL MODE
MUTE
MULTIBIT MODULATOR
DAC
ANALOG FILTER
OUTPUT BUFFER ANALOG OUTPUTS
MUTE
MULTIBIT MODULATOR
DAC
ANALOG FILTER
OUTPUT BUFFER
4 DE-EMPHASIS MUTE POWER-DOWN/RESET ANALOG SUPPLY
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD1857/AD1858-SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock (FMCLK) Input Signal Input Sample Rate Measurement Bandwidth AD1857 Input Data Wordwidth AD1858 Input Data Wordwidth Load Capacitance Load Impedance Input Voltage HI (VIH) Input Voltage LO (VIL)
+5.0 V 25C 11.2896 MHz (256 x FS Mode) 1.0013 kHz -0.5 dB Full Scale 44.1 kHz 20 Hz to 20 kHz 18 Bits 16 Bits 100 pF 47 k 2.4 V 0.8 V
I2S-Justified Mode (Ref. Figure 7) for AD1857, Right-Justified Mode (Ref. Figure 8) for AD1858. Performance of the right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Values in bold typeface are tested, all others are guaranteed, not tested.
ANALOG PERFORMANCE Min Typ Max Units
AD1857 Resolution AD1858 Resolution Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No A-Weight Filter With A-Weight Filter Total Harmonic Distortion + Noise Analog Outputs Single-Ended Output Range ( Full Scale) Output Impedance at Each Output Pin Output Capacitance at Each Output Pin Out-of-Band Energy (0.5 x FS to 100 kHz) CMOUT DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ method) Interchannel Phase Deviation Mute Attenuation De-emphasis Gain Error
DIGITAL I/O Min
18 16 91 94 -90 0.003 2.8 3.0 <200
Bits Bits dB dB dB % V p-p pF dB V % dB ppm/C dB Degrees dB dB
-85 0.006 3.2 20 -72.5 2.4 7.5 0.2 300 -100 -90 0.1
2.1
2.25 3.0 0.01 150 -120 0.1 -100
Max
Units
Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) Input Capacitance
2.4 0.8 10 10 20
V V A A pF
-2-
REV. 0
AD1857/AD1858
DIGITAL TIMING (Guaranteed over 0C to +70C, AVDD = DVDD = +5.0 V 5%) Min Max Units
tDML tDMH tDMP tDML tDMH tDMP tDBH tDBL tDBP tDLS tDLH tDDS tDDH tPDRP
MCLK LO Pulse Width (256 x FS Mode) MCLK HI Pulse Width (256 x FS Mode) MCLK Period (256 x FS Mode) MCLK LO Pulse Width (384 x FS Mode) MCLK HI Pulse Width (384 x FS Mode) MCLK Period (384 x FS Mode) BCLK HI Pulse Width BCLK LO Pulse Width BCLK Period LRCLK Setup LRCLK Hold SDATA Setup SDATA Hold PD/RST LO Pulse Width
35 40 88.577 25 25 59.0514 20 20 354.308 20 5 5 10 4 MCLK Periods (355 ns @ 11.2896 MHz)
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
POWER Min Typ Max Units
Supplies Voltage, Analog and Digital Analog Current Analog Current - Power-Down Digital Current Digital Current - Power-Down Dissipation Operation - Both Supplies Operation - Analog Supply Operation - Digital Supply Power-Down - Both Supplies Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins
TEMPERATURE RANGE
4.75
5 35 30 20 5 275 175 100 25 -60 -50
5.25 40 60 25 11 325 200 125 56
V mA A mA mA mW mW mW mW dB dB
Min
Typ
Max
Units
Specifications Guaranteed Functionality Guaranteed Storage
ABSOLUTE MAXIMUM RATINGS*
25 0 -55 70 125
C C C
Min
Typ
Max
Units
DVDD to DGND AVDD to AGND Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering
-0.3 6 -0.3 6 DGND - 0.3 DVDD + 0.3 AGND - 0.3 AVDD + 0.3 -0.3 0.3 Indefinite Short Circuit to Ground +300 10
V V V V V C sec
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
REV. 0
-3-
AD1857/AD1858
PACKAGE CHARACTERISTICS Min Typ Max Units
JA (Thermal Resistance [Junction-to-Ambient]) JC (Thermal Resistance [Junction-to-Case])
DIGITAL FILTER CHARACTERISTICS Min
195 13
C/W C/W
Max
Units
Passband Ripple Stopband1 Attenuation 48 kHz FS Passband Stopband 44.1 kHz FS Passband Stopband 32 kHz FS Passband Stopband Other FS Passband Stopband Group Delay Group Delay Variation
ANALOG FILTER CHARACTERISTICS
0.045 62 0 26.688 0 24.520 0 17.792 0 0.556 21.312 6117 19.580 5620 14.208 4078 0.444 127.444 40/FS 0
dB dB kHz kHz kHz kHz kHz kHz FS FS sec s
Min
Typ
Max
Units
Passband Ripple Stopband Attenuation (at 64 x FS)
-0.075 58
dB dB
NOTES 1 Stopband nominally repeats itself at multiples of 128 x FS, where FS is the input word rate. Thus the digital filter will attenuate to 62 dB across the frequency spectrum, except for a range 0.55 x FS wide at multiples of 128 x FS. Specifications subject to change without notice.
ORDERING GUIDE Model Temperature Package Description Package Option*
PIN CONFIGURATION
MCLK 1 PD/RST 2 20 SDATA 19 BCLK 18 LRCLK
AD1857JRS AD1857JRSRL AD1858JRS AD1858JRSRL
0C to +70C 0C to +70C 0C to +70C 0C to +70C
20-Lead SSOP 20-Lead SSOP 20-Lead SSOP 20-Lead SSOP
RS-20 RS-20 on 13" Reels RS-20 RS-20 on 13" Reels
MODE 3 NC 4 DEEMP 5 384/256 6 AVDD
AD1857 AD1858
17 DVDD 16 DGND
TOP VIEW 15 MUTE (Not to Scale) 14 AVDD 7 13 OUTR 12 AGND 11 FILT
OUTL 8 AGND 9 CMOUT 10
*RS = Shrink Small Outline
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1857/AD1858 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. 0
AD1857/AD1858
PIN LIST Digital Audio Serial Input Interfaces Pin Name Number I/O Description
SDATA BCLK LRCLK MODE
20 19 18 3
I I I I
Serial input, MSB first, containing two channels of 16, 18 or 20 bits (AD1857) or 16 bits (AD1858) of twos complement data per channel. Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion. Left/right clock input for input data. Must run continuously. Input serial data port mode control. Selects between I2S-justified (HI) and left-justified (LO) on the AD1857. Selects between DSP serial port style mode (HI) and rightjustified (LO) on the AD1858. The state of the mode pin should be changed only when the AD1857/AD1858 is held in reset (PD/RST LO). Otherwise, the AD1857/ AD1858 serial port may lose synchronism.
Control and Clock Signals Pin Name Number I/O Description
PD/RST
2
I
DEEMP
5
I
MUTE MCLK
15 1
I I
384/256
6
I
Power-Down/Reset. The AD1857/AD1858 are placed in a low power consumption "sleep" mode when this pin is held LO. The AD1857/AD1858 are reset on the rising edge of this signal. Connect HI for normal operation. De-emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to impose a 50/15 s response characteristic on the output audio spectrum at an assumed 44.1 kHz sample rate. Mute. Assert HI to mute both stereo analog outputs of the AD1857/AD1858. Deassert LO for normal operation. Master Clock Input. Connect to an external clock source at either 256 or 384 times the intended sample frequency as determined by the 384/256 pin. Must be synchronous with LRCLK, but may have any phase with respect to LRCLK. Selects the master clock mode as either 384 times the intended sample frequency (HI) or 256 times the intended sample frequency (LO). The state of this input should be hardwired to logic LO or logic HI or may be changed while the AD1857/ AD1858 is in power-down/reset. It must not be changed while the AD1857/AD1858 is operational.
Analog Signals Pin Name Number I/O Description
FILT CMOUT
11 10
O O
OUTL OUTR
8 13
O O
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 F and 0.1 F capacitors to the AGND pin. Voltage Reference Common Mode Output. Should be decoupled with 10 F capacitor to the AGND pin or plane. This output is available externally for dc coupling and level-shifting. CMOUT should not have any signal dependent load, or used where it will sink or source current. Left channel line level analog output. Right channel line level analog output.
Power Supply Connections and Miscellaneous Pin Name Number I/O Description
AVDD AGND DVDD DGND N/C
7, 14 9, 12 17 16 4
I I I I
Analog Power Supply. Connect to analog +5 V supply. Analog Ground. Digital Power Supply. Connect to digital +5 V supply. Digital Ground. No Connect. Reserved. Do not connect.
REV. 0
-5-
AD1857/AD1858
DEFINITIONS Dynamic Range Interchannel Gain Mismatch
The ratio of a full-scale output signal to the integrated output noise in the passband (0 kHz to 20 kHz), expressed in decibels (dB). Dynamic range is measured with a -60 dB input signal and is equal to (S/[THD+N]) + 60 dB. Note that spurious harmonics are below the noise with a -60 dB input, so the noise level establishes the dynamic range. This measurement technique is consistent with the recommendations of the Audio Engineering Society (AES17-1991) and the Electronic Industries Association of Japan (EIAJ CP-307).
Total Harmonic Distortion + Noise (THD+N)
With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels.
Gain Drift
Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a zero input, to a fullscale 1 kHz sine-wave input on the other channel, expressed in decibels.
Interchannel Phase Deviation
The ratio of the root-mean-square (rms) value of a full-scale fundamental input signal to the rms sum of all other spectral components in the passband, expressed in decibels (dB) and as a percentage.
Passband
Difference in output sampling times between stereo channels, expressed as a phase difference in degrees between 1 kHz inputs.
Power Supply Rejection
The region of the frequency spectrum unaffected by the attenuation of the digital interpolation filter.
Passband Ripple
With zero input, signal present at the output when a 300 mV p-p signal is applied to power supply pins, expressed in decibels of full scale.
Group Delay
The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the passband, expressed in decibels.
Stopband
Intuitively, the time interval required for an input pulse to appear at the converter's output, expressed in seconds(s). More precisely, the derivative of radian phase with respect to radian frequency at a given frequency.
Group Delay Variation
The region of the frequency spectrum attenuated by the digital interpolation filter to the degree specified by "stopband attenuation."
Gain Error
The difference in group delays at different input frequencies. Specified as the difference between the largest and the smallest group delays in passband, expressed in microseconds (s).
De-Emphasis Gain Error
With a near full-scale input, the ratio of actual output to expected output, expressed as a percentage.
A measure, expressed in decibels, of the difference between the ideal 50/15 s de-emphasis filter response, and the actual 50/15 s de-emphasis filter response.
-6-
REV. 0
AD1857/AD1858 Typical Performance Characteristics
Figures 1 through 4 illustrate the typical performance of the AD1857/AD1858 as measured by an Audio Precision System Two. Signal-to-Noise (dynamic range) THD+N performance is shown under a range of conditions. Figure 5 shows the power supply rejection performance of the AD1857/AD1858. The channel separation performance of the AD1857/AD1858 is shown in Figure 6. The digital filter transfer function is shown in Figure 7.
0 -10 -20 -30 -40 -50 -60
dBr A
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
-70 -80 -90 -100 -110 -120 -130 -140 -150 0 2.5 5.0 7.5 10.0 kHz 12.5 15.0 17.5 20.0
dBr A
0
2.5
5.0
7.5
10.0 kHz
12.5
15.0
17.5
20.0
Figure 1. 1 kHz Tone at -0.5 dBFS
Figure 3. THD+N vs. Frequency at -0.5 dBFS
0 -10 -20 -30 -40 -50
0 -10 -20 -30 -40 -50
dBr A
-70 -80 -90 -100 -110 -120 -130 -140 0 2.5 5.0 7.5 10.0 kHz 12.5 15.0 17.5 20.0
dBr A
-60
-60 -70 -80 -90 -100 -110 -120 -130 -140 -100 -80 -60 dBFS -40 -20 0
Figure 2. 1 kHz Tone at -10 dBFS
Figure 4. THD+N vs. Amplitude at 1 kHz
REV. 0
-7-
AD1857/AD1858 Typical Performance Characteristics (continued)
-40 -45 -50 -52 -55
dBr A
-40 -44 -48
0 -10 -20 -30 -40 -50 dBr B -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2.5 5.0 7.5 10.0 kHz 12.5 15.0 17.5 20.0
LEFT CHANNEL RIGHT CHANNEL
-56 -60 -64 -68
dBr A
-60 -65 -70
-72 -75 -80 0 2.5 5.0 7.5 10.0 kHz 12.5 15.0 17.5 -76 -80 20.0
Figure 5. Power Supply Rejection to 300 mV p-p on AVDD
Figure 6. Channel Separation vs. Frequency at -0.5 dBFS
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 0.0
dBFS
0.5
1.0
1.5 FS
2.0
2.5
3.0
3.5
Figure 7. Digital Filter Signal Transfer Function to 3.5
FS
-8-
REV. 0
AD1857/AD1858
THEORY OF OPERATION
The AD1857/AD1858 offer the advantages of sigma-delta conversion architectures (no component trims, low cost CMOS process technology, superb low-level linearity performance) with the advantages of conventional multibit R-2R resistive ladder audio DACs (continuously variable sample rate support, jitter tolerance, very low output noise, etc.). The use of a multibit sigma-delta modulator means that the AD1857/AD1858 generate dramatically lower amounts of outof-band noise energy, which greatly reduces the requirement on post DAC filtering. The required post-filtering is integrated on the AD1857/AD1858. The AD1857/AD1858's multibit sigmadelta modulator is also highly immune to digital substrate noise.
Serial Audio Data Interface
The conventional problem limiting the performance of multibit sigma-delta converters is the nonlinearity of the passive circuit elements used to sum the quantization levels. Analog Devices has developed (and received patents on) a revolutionary architecture that overcomes the circuit element linearity problem that otherwise limits the performance of multibit sigma-delta audio converters. This new architecture provides the AD1857/AD1858 with the same excellent differential nonlinearity and linearity drift (over temperature and time) specifications as single bit sigma-delta DACs. The AD1857/AD1858's multibit modulator has another important advantage; it has a high immunity to substrate digital noise. Substrate noise can be a significant problem in mixedsignal designs, where it can produce intermodulation products that fold down into the audio band. The AD1857/AD1858 are approximately eight times less sensitive to digital substrate noise (voltage reference noise injection) than equivalent single-bit sigma-delta modulator based DACs.
Dither Generator
The serial audio data interface uses the bit clock (BCLK) simply to clock the data into the AD1857/AD1858. The bit clock may therefore be asynchronous to the L/R clock. The left/right clock (LRCLK) is both a framing signal and the sample frequency input to the interpolation filter. The left/right clock must be synchronous with MCLK, but may have any phase relationship with respect to MCLK; LRCLK is generally synchronously divided down from MCLK. The SDATA input carries the serial stereo digital audio in MSB first, twos-complement format.
Digital Interpolation Filter
The purpose of the interpolator is to "oversample" the input data, i.e., to increase the sample rate so the first signal image is moved out to the oversample frequency, which relaxes the attenuation requirements on the analog reconstruction filter. The AD1857/AD1858 interpolator increases the input data sample rate by 128. The interpolation is performed using a multistage FIR digital filter structure. The first stage is a droop equalizer; the second and third stages are halfband filters; and the fourth stage is a second-order comb filter. The FIR filter implementation is multiplier-free, i.e., the multiplies are performed using shift-and-add operations. The FIR filter coefficients have been recoded in a canonical sign digit format to enable the use of a compact arithmetic logic unit without a multiplier.
Multibit Sigma-Delta Modulator
The AD1857/AD1858 include an on-chip dither generator that is intended to further "whiten" the quantization noise introduced by the multibit DAC. The dither has a triangular Probability Distribution Function (PDF) characteristic, which is generally considered to create the most favorable noise shaping of the residual quantization noise. The AD1857/AD1858 are among the first low cost IC audio DACs to include dithering.
Analog Filtering
The AD1857/AD1858 include a second-order switched capacitor discrete time low-pass filter followed by a first-order analog continuous time low-pass filter. These filters eliminate the need for any additional off-chip external reconstruction filtering. This on-chip switched capacitor analog filtering is essential to reduce the deleterious effects of master clock jitter.
Digital De-Emphasis Processing
The AD1857/AD1858 employ a 4-bit second-order sigma-delta modulator. Whereas a traditional single-bit sigma-delta modulator has two levels of quantization, the AD1857/AD1858's has 17 levels of quantization. Traditional single-bit sigma-delta modulators sample the input signal at 64 times the input sample rate; the AD1857/AD1858 sample the input signal at 128 times the input sample rate. The additional quantization levels combined with the high oversampling ratio means that the AD1857/AD1858 DAC output spectrum contains dramatically lower levels of out-of-band noise energy, which is a major stumbling block with more traditional single-bit sigma-delta architectures. This means that the post-DAC analog reconstruction filter has reduced transition band steepness and attenuation requirements, which directly equates to lower phase distortion. Since the analog filtering generally establishes the noise and distortion characteristic of the DAC, the reduced requirements translate into better audio performance. Multibit sigma-delta modulators bring an additional benefit: they are essentially free of stability (and therefore potential loop oscillation) problems. They are able to scale the output signal to a wider range of the voltage reference, which can increase the overall dynamic range of the converter. REV. 0 -9-
The AD1857/AD1858 include digital circuitry for implementing the 50/15 s de-emphasis frequency response characteristic. A control pin DEEMP (Pin 5) enables de-emphasis when it is asserted HI. The digital de-emphasis response assumes a sample frequency of 44.1 kHz. The transfer function magnitude error of this digital filter is less than 0.1 dB (from 0 kHz to 20 kHz) compared to a 50/15 s continuous time filter. If the sample frequency is not 44.1 kHz, the de-emphasis frequency response will scale directly with frequency. The 44.1 kHz FS digital deemphasis frequency response is shown in Figure 8.
T1 = 50s 0
GAIN - dB
T2 = 15s -10
F2 F1 10.61 3.183 FREQUENCY - kHz
Figure 8. Digital De-Emphasis Frequency Response
AD1857/AD1858
OPERATING FEATURES Serial Data Input Port Serial Input Port Modes
The AD1857/AD1858 use the frequency of the left/right and master input clocks to determine the input sample rate. Generally, the master clock (MCLK) is divided down to synthesize the left/right clock (LRCLK). LRCLK must run continuously and transition twice per stereo sample period (except in the leftjustified DSP serial port style mode, when it transitions four times per stereo sample period). The bit clock (BCLK) is edgesensitive and may be used in a gated or burst mode, i.e., a stream of pulses during data transmission followed by periods of inactivity. The bit clock is only used to write the audio data into the serial input port. It is important that the left/right clock is "clean," with monotonic rising and falling edge transitions and no excessive overshoot or undershoot that could cause false clock triggering of the AD1857/AD1858. The AD1857/AD1858's flexible serial data input port accepts data in twos-complement, MSB first format. The left channel data field always precedes the right channel data field. The input data consists of 16, 18 or 20 bits (16 bits only to the AD1858). All digital inputs are specified to TTL logic levels. The input data port is configured by a control pin, MODE, Pin 3. The AD1857 and the AD1858 are identical except for the serial data input port modes offered. The AD1857 offers I2S-justified and left-justified modes, for 16-, 18- or 20-bit data words. The AD1858 offers right-justified and DSP serial port style mode for 16-bit data words. Note: During the first 30,000 MCLK cycles after coming out of reset, the AD1857/AD1858 synchronizes its internal sequencer counter to the incoming LRCLK. After this period of time, it is assumed that the LRCLK and the internal AD1857/AD1858 output channels could be switched (L to R and R to L). Therefore, if the incoming LRCLK is stopped and then restarted with a different phase, the AD1857/AD1858 should be reset again to synchronize with this new clock.
LRCLK INPUT BCLK INPUT SDATA INPUT
MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB
The AD1857/AD1858 use an input pin to control the mode configuration of the input data port. MODE (Pin 3) programs the input data port mode as follows: Figure 9 shows the AD1857 left-justified mode. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay. The left-justified mode can be used in the 16-, 18- or 20-bit input mode.
MODE (Pin 3) AD1857 Serial Input Port Mode
LO HI
Left-Justified (See Figure 9) I2S-Justified (See Figure 10)
MODE (Pin 3)
AD1858 Serial Input Port Mode
LO HI
Right-Justified (See Figure 11) Left-Justified DSP Serial Port Style (See Figure 12)
Figure 10 shows the AD1857 I2S-justified mode. LRCLK is LO for the left channel, and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition, but with a single BCLK period delay. The I2S-justified mode can be used in the 16-, 18- or 20-bit input mode. Figure 11 shows the AD1858 the right-justified mode. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is delayed 16-bit clock periods from an LRCLK transition so that when there are 64 BCLK periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition.
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB-1
MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
Figure 9. AD1857 Left-Justified Mode
LRCLK INPUT BCLK INPUT SDATA INPUT
MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 10. AD1857 I 2S-Justified Mode
LRCLK INPUT BCLK INPUT SDATA INPUT
LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB
LEFT CHANNEL
RIGHT CHANNEL
Figure 11. AD1858 Right-Justified Mode
-10-
REV. 0
AD1857/AD1858
LRCLK INPUT BCLK INPUT SDATA INPUT
MSB MSB-1 LSB+2 LSB+1 LSB MSB MSB-1 LSB+2 LSB+1 LSB MSB MSB-1
LEFT CHANNEL
RIGHT CHANNEL
Figure 12. AD1858 Left-Justified DSP Serial Port Style
LRCLK INPUT BCLK INPUT SDATA INPUT
LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1
LEFT CHANNEL
RIGHT CHANNEL
Figure 13. AD1857/AD1858 32
FS Packed Mode
Figure 12 shows the AD1858 left-justified DSP serial port style mode. LRCLK must pulse HI for at least one bit clock period before the MSB of the left channel is valid, and LRCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data is valid on the falling edge of BCLK. Note that in this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse, the right data is transmitted with the second LRCLK pulse, and synchronism is maintained from that point forward. Note that in 16-bit input mode, the AD1857/AD1858 are capable of a 32 x FS BCLK frequency "packed mode" where the MSB is left-justified to an LRCLK transition, and the LSB is right-justified to an LRCLK transition. LRCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. Packed mode can be used when the AD1857 is programmed in left-justified mode, or when the AD1858 is programmed in right-justified mode. Packed mode is shown in Figure 13.
Master Clock
found within 1024 input sample periods (approximately 23 milliseconds at 44.1 kHz), the output is muted regardless.
Output Drive, Buffering and Loading
The AD1857/AD1858 analog output stage is able to drive a 2 k load. If lower impedance loads must be driven, an external buffer stage such as the Analog Devices SSM2142 should be used. The analog output is generally ac coupled with a 10 F capacitor as shown in Figure 21. It is possible to dc couple the AD1857/AD1858 output into an op amp stage using the CMOUT signal as a bias point.
On-Chip Voltage Reference
The synchronous master clock of the AD1857/AD1858 is supplied by an external clock source applied to MCLK. Figure 14 shows example connections. Do not change the state of the 384/256 pin while the AD1857/AD1858 is operational; this pin should be hardwired LO or HI. Alternatively, its state may be changed while the PD/RST pin is asserted LO.
MCLK FREQUENCY 12.288MHz 11.2896MHz 8.192MHz 256 MODE 384/256 = LO 18.432MHz 16.9344MHz 12.288MHz 384 MODE 384/256 = HI SAMPLE RATE 48kHz 44.1kHz 32kHz
The AD1857/AD1858 include an on-chip voltage reference that establishes the output voltage range. The nominal value of this reference is +2.25 V, which corresponds to a line output voltage swing of 3 V p-p. The line output signal is centered around a voltage established by the CMOUT (common-mode output) (Pin 10). The reference must be bypassed both on the FILT input (Pin 11) with 10 F and 0.1 F capacitors, and on the CMOUT output (Pin 10) with 10 F and 0.1 F capacitors, as shown in Figure 21. Both the FILT pin and the CMOUT pin use the AGND ground. The on-chip voltage reference may be overdriven with an external reference source by applying this voltage to the FILT pin. CMOUT and FILT must still be bypassed as shown in Figure 21. An external reference can be useful to calibrate multiple AD1857/AD1858 DACs to the same gain. Reference bypass capacitors larger than those suggested can be used to improve the signal-to-noise performance of the AD1857/AD1858.
Power-Down and Reset
1 MCLK
6 384/256
Figure 14. AD1857/AD1858 Clock Connections
Digital Mute
The AD1857/AD1858 offer a control pin that mutes the analog output. By asserting the MUTE (Pin 15) signal HI, both the left channel and the right channel are muted. The AD1857/ AD1858 have been designed to minimize pops and clicks when muting and unmuting the device. The AD1857/AD1858 include a zero crossing detector which attempts to implement mute on waveform zero crossings only. If a zero crossing is not REV. 0
The PD/RST input (Pin 2) is used to control the power consumed by the AD1857/AD1858. When PD/RST is held LO, the AD1857/AD1858 are placed in a low dissipation power-down state. When PD/RST is brought HI, the AD1857/AD1858 become ready for normal operation. The master clock (MCLK, Pin 1) must be running for a successful reset or power-down operation to occur. The PD/RST signal must be LO for a minimum of four master clock periods (326 ns with a 12.288 MHz MCLK frequency). When the PD/RST input (Pin 2) is brought HI, the AD1857/ AD1858 are reset. All registers in the AD1857/AD1858 digital engine (serial data port, interpolation filter and modulator) are zeroed, and the amplifiers in the analog section are shorted during the reset operation. The AD1857/AD1858 have been designed to minimize pops and clicks when entering and exiting the power-down state. -11-
AD1857/AD1858
Control Signals
The MODE and DEEMP control inputs are normally connected HI or LO to establish the operating state of the AD1857/AD1858. They can be changed dynamically (and asynchronously to the LRCLK and the master clock) as long as they are stable before the first serial data input bit (i.e., the MSB) is presented to the AD1857/AD1858.
APPLICATION ISSUES Interface to MPEG Audio Decoders
Figure 18 shows the suggested interface to the Philips SAA2500* MPEG audio decoder IC. The SAA2500 supports 18 bits of data using an I2S-compatible output format.
SCK 19 BCLK 18 LRCLK 20 SDATA HI HI 3 6 1 256 x Fs MODE 384/256 MCLK
SAA2500
WS SD
FSCLKIN
AD1857
Figure 15 shows the suggested interface to the Analog Devices ADSP-21xx family of DSP chips, for which several MPEG audio decode algorithms are available. The ADSP-21xx supports 16 bits of data using a left-justified DSP serial port style format.
SCLK RFS NC 19 BCLK 18 LRCLK 20 SDATA HI NC HI 3 MODE 6 384/256 1 MCLK
Figure 18. Interface to SAA2500
Figure 19 shows the suggested interface to the Zoran ZR38000* DSP chip, which can act as an MPEG audio or AC-3 audio decoder. The ZR38000 supports 16 bits of data using a leftjustified output format.
SCKB WSB 19 BCLK 18 LRCLK 20 SDATA LO HI 3 MODE
ADSP-21xx
TFS DT DR
AD1858
ZR38000
SDB SCKIN
NC = NO CONNECT
AD1857
Figure 15. Interface to ADSP-21xx
6 384/256 1 MCLK
Figure 16 shows the suggested interface to the Texas Instruments TMS320AV110* MPEG audio decoder IC. The TMS320AV110 supports 18 bits of data using a right-justified output format.
SCLK 19 BCLK 18 LRCLK 20 SDATA HI HI 3 6 1 256 x Fs MODE 384/256 MCLK
256 x Fs
Figure 19. Interface to ZR38000
TMS320AV110
LRCLK PCMDATA PCMCLK
Figure 20 shows the suggested interface to the C-Cube Microsystems CL480* MPEG system decoder IC. The CL480 supports 16 bits of data using a right-justified output format.
AD1858
DA-BCK 19 BCLK 18 LRCLK 20 SDATA HI HI 3 6 1 256 x Fs MODE 384/256 MCLK DA-LRCK DA-DATA DA-XCK
CL480
AD1858
Figure 16. Interface to TMS320AV110
Figure 17 shows the suggested interface to the LSI Logic L64111* MPEG audio decoder IC. The L64111 supports 16 bits of data using a left-justified output format.
Figure 20. Interface to CL480
SCLKO LRCLKO 19 BCLK 18 LRCLK 20 SDATA LO LO 3 6 1 384 x Fs MODE 384/256 MCLK
L64111
SERO SYSCLK
AD1857
Figure 17. Interface to L64111
*All trademarks are properties of their respective holders.
-12-
REV. 0
AD1857/AD1858
Layout and Decoupling Considerations
The recommended decoupling, bypass and output circuits for the AD1857/AD1858 are shown in Figure 21.
PCB and Ground Plane Recommendations
MCLK 1 PD/RST 2 MODE 3 NC 4 DEEMP 5 384/256 6 AVDD 7 OUTL 8 AGND 9 CMOUT 10 NC = NO CONNECT
20 SDATA 19 BCLK
The AD1857/AD1858 ideally should be located above a split ground plane, with the digital pins over the digital ground plane and the analog pins over the analog ground plane. The split should occur between Pins 6 and 7, and between Pins 14 and 15 as shown in Figure 22. The ground planes should be linked with a ferrite bead. This ground plane strategy maximizes the AD1857/AD1858's analog audio performance.
DIGITAL GROUND PLANE
18 LRCLK 17 DVDD 16 DGND 15 MUTE 14 AVDD FERRITE BEAD
ANALOG GROUND PLANE
13 OUTR 12 AGND 11 FILT
Figure 22. Recommended Ground Plane
MCLK FREQUENCY +5V ANALOG 4.7F +5V ANALOG 4.7F 12.288MHz 11.2896MHz 8.192MHz 256 MODE 384/256 = LO 0.1F 0.1F 14 AVDD 1 MCLK 18.432MHz 16.9344MHz 12.288MHz 384 MODE 384/256 = HI
SAMPLE RATE 48kHz 44.1kHz 32kHz
7 AVDD
9 AGND
6 384/256 FILT 11 0.1F AGND 12 4.7F
20 SDATA 19 BLCK DSP OR AUDIO DECODER 18 LRCLK OUTL 3 MODE DVDD 17 0.01F 4.7F CONTROLLER OUTL +5V DIGITAL NC = NO CONNECT OUTR 13 8 DGND 16 NC 4 PD/RST 2 MUTE 15 8* 2.2F OUTR 13 * DEEMP 5
AD1857/AD1858
CMOUT 10 2.2F
BIAS VOLTAGE FOR EXTERNAL USE LEFT LINE OUTPUT RIGHT LINE OUTPUT
*OPTIONAL OUTPUT FILTER 2.2F 1k + 820pF 2.2F 1k + 820pF 100k 100k LEFT LINE OUTPUT
RIGHT LINE OUTPUT
Figure 21. Recommended Circuit Connection
REV. 0
-13-
AD1857/AD1858
Timing Diagrams
The serial data port timing is shown in Figures 23 and 24. The minimum bit clock HI pulse width is tDBH and the minimum bit clock LO pulse width is tDBL. The minimum bit clock period is tDBP. The left/right clock minimum setup time is tDLS and the left/right clock minimum hold time is tDLH. The serial data
tDBH
BCLK
minimum setup time is tDDS and the minimum serial data hold time is tDDH. The power-down/reset timing is shown in Figure 25. The minimum reset LO pulse width is tPDRP (four MCLK periods) to accomplish a successful AD1857/AD1858 reset operation.
tDBP
tDBL tDLS
LRCLK
SDATA LEFT-JUSTIFIED MODE
tDDS
MSB MSB-1
AD1857
SDATA I2S-JUSTIFIED MODE
tDDH tDDS
MSB
AD1857
SDATA RIGHT-JUSTIFIED MODE
tDDH tDDS
MSB
tDDS
LSB
AD1858
tDDH
tDDH
Figure 23. Serial Data Port Timing
tDBH
BCLK
tDBP
tDLS
LRCLK
tDBL
tDLH tDDS
MSB MSB-1
SDATA LEFT-JUSTIFIED DSP SERIAL PORT STYLE MODE
AD1858
tDDH
Figure 24. Serial Data Port Timing-DSP Serial Port Style Mode (AD1858 Only)
MCLK
PD/RST
tPDRP
Figure 25. Power-Down/Reset Timing
-14-
REV. 0
AD1857/AD1858
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead SSOP (RS-20)
0.295 (7.50) 0.271 (6.90)
20
11
0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64)
1
10
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.78) 0.066 (1.67)
0.008 (0.203) 0.002 (0.050)
0.0256 (0.65) BSC
SEATING PLANE
0.009 (0.229) 0.005 (0.127)
8 0
0.037 (0.94) 0.022 (0.559)
1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
REV. 0
-15-
-16-
C2218-12-4/97
PRINTED IN U.S.A.

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